A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the typical case. The power consumption of the DLL is 2.6mW at 1.2GHz and 0.366mW at 600 kHz with 1.0V power supply. The measured r.m.s jitter and peak-to-peak jitter at 1.2GHz are 3.38 ps and 39.29 ps, respectively.